1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing and, more particularly to a wafer level stack chip package using a redistribution substrate and redistribution semiconductor chips and a method for manufacturing such a stack chip package.
2. Description of Related Art
Recent trends in electronics have been developed toward miniaturization, i.e., smaller and thinner chips. In order to satisfy these pressing demands, a chip scale package manufactured at wafer level using a redistribution technique has been introduced.
This package is referred to as a wafer level chip scale package (WLCSP). As described above, the WLCSP employs a redistribution technique, which reroutes electrode pads on the chip to bigger pads in different positions. External connection terminals such as solder balls may be formed on the rerouted pads. In WLCSP, a series of package manufacturing processes are carried out under wafer level.
As is well known, the conventional semiconductor wafer comprises many integrated circuit chips on a silicon substrate. FIG. 1 schematically shows a conventional semiconductor wafer 10. FIG. 2 is an enlarged plan view of a portion xe2x80x9cAxe2x80x9d of FIG. 1. As shown in FIGS. 1 and 2, the wafer 10 comprises a plurality of integrated circuit chips 20 and scribing areas 14 for separating an integrated circuit chip 20 from other integrated circuit chips 20. Chip pads 22 serving as I/O terminals are formed on each chip 20. A passivation layer 24 such as a nitride layer may be coated on the whole surface of the chip 20 except for the chip pads 22.
FIG. 3 is a plan view of conventional redistribution wafer level chip scale packages 30. As shown in FIG. 3, external connection terminals 36 are disposed on different positions from the chip pads 22 of FIG. 2. The chip pads 22 are rerouted into different positions by the redistribution process, and the external connection terminals 36 are attached to the rerouted pads. After finishing the manufacturing of the packages at the wafer level, the wafer 10 is cut into a plurality of unit packages 30 along the scribing areas 14.
FIG. 4 is a sectional view of the redistribution wafer level chip scale package 30 of FIG. 3. As shown in FIG. 4, the chip pads 22 and the passivation layer 24 are formed on the upper surface of a semiconductor substrate 12. A first polymeric layer 31 is formed on the passivation layer 24, and serves as a stress buffer and an electrically dielectric layer. An under barrier metal (UBM) layer 32 is deposited on the chip pads 22 and the first polymeric layer 31. A redistribution layer 33 is formed on the UBM layer 31, and a second polymeric layer 34 is formed on the redistribution layer 33. The second polymeric layer 34 serves to protect the redistribution layer 33 from the external environment. Herein, the second polymeric layer 34 is partially removed, thereby exposing the redistribution layer 33. An UBM layer 35 is deposited on the exposed redistribution layer 33, and the external connection terminal 36 is mounted thereon.
The above-described conventional wafer level chip scale package comprises a thin polymeric layer, thereby reducing electrical performance. Further, due to the increase of the number of the chip pads and the decrease of the pitch between the chip pads, fan-in and fan-out are not easily achieved.
The conventional wafer level chip scale package comprising the external connection terminals on its one surface, i.e. the first surface, can be stacked on other wafer level chip scale package, but the electrical connection between the stacked chip scale packages is not easy. That is, the first surface of the upper chip scale package is to be stacked on the other surface, i.e., the second surface of the lower chip scale package. At this time it is difficult to electrically interconnect the external connection terminals of the upper chip scale package to the external connection terminals of the lower chip scale package.
The stack chip scale package manufactured by stacking the wafers reduces wafer yield and stack package yield. Just one failed chip among the chips of the stack package causes the stack chip scale package to be detected as a failure, thereby reducing the yield of the stack chip package.
Accordingly, a goal is to provide a stack chip package manufactured by three-dimensionally stacking wafer level chip packages and a manufacturing method for same.
Another goal is to improve the yield of the wafer level stack chip package.
Still another goal is to prevent the deterioration of the electrical properties due to the conventional thin polymeric layer.
Yet another goal is to provide the wafer level stack chip package, which properly achieves fan-in and/or fan-out.
In order to achieve these foregoing and other objects, the present invention is directed to a wafer level stack chip package formed by three-dimensionally stacking a plurality of semiconductor chips. The wafer level chip package comprises a redistrubution substrate, at least one lower semiconductor chip stacked on the redisctribution substrate, and an uppermost semiconductor chip. The redistribution substrate may comprise a first dielectric layer in a pre-determined pattern, a redistribution layer formed on the first dielectric layer, a second dielectric layer formed on the first dielectric layer and the redistribution layer, and substrate pads connected to the redistribution layer. The lower semiconductor chip is stacked on the redistribution layer and may comprise a semiconductor substrate, a passivation layer formed on the upper surface of the substrate, a plurality of chip pads exposed from the passivation layer, a redistribution layer formed on the passivation layer and electrically connected to the chip pads, a polymeric layer formed on the passivation and layer and the redistribution layer, and having through holes for partially exposing the redistribution layer, the through holes corresponding to the substrate pads, and having conductive filling material filling the through holes, and inner connection terminals formed on and electrically connected to the exposed redistribution layer via the through holes. The uppermost semiconductor chip may comprise the same elements as the lower semiconductor chip, and may be flip chip bonded to the through holes. The package may further comprise a filling layer for filling areas between chips, a metal lid for coating most of the external surfaces, and external connection terminals formed on and electrically connected to the exposed redistribution layer from the first dielectric layer of the redistribution substrate.
Further, the present invention provides a method for manufacturing the above-described wafer level stack chip package.